Téléchargez le livre : Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog

Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog

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Paru le : 2000

Explaining how you can write Verilog to describe chip designs at the RT-level in a manner that co-operates with verification processes, this text focuses on how this co-operation can return an order of magnitude improvement in performance and capacity from tools such as simulation and equivalence c...
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Description du livre


Explaining how you can write Verilog to describe chip designs at the RT-level in a manner that co-operates with verification processes, this text focuses on how this co-operation can return an order of magnitude improvement in performance and capacity from tools such as simulation and equivalence checkers. It reduces the labour costs of coverage and formal model checking by facilitating communication between the design engineer and the verification engineer. It also orients the RTL style to provide more useful results from the overall verification process.

À propos

Auteur
H. Foster , K. Pickavance , L. Bening
Éditeur
Kluwer Academic Publishers
Collection
n.c
Parution
2000
Pages
n.c
EAN papier
0306470160

Caractéristiques détaillées - droits

EAN PDF
0306470160
Prix
132,25 €
Nombre pages copiables
1
Nombre pages imprimables
10
Taille du fichier
1445 Ko
Ce livre est accessible aux handicaps informations d'accessibilité

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